High Speed Interface
HDMI 1.4b Transceiver Phy &Link silicon proven IP
- Maximum Resolution support : 4K x 2K (3840x2160) pixels @24/25/30Hz
- UD(4K) TV support : 4K x 2K (4096x2160) pixels @24Hz
- 3D Video support: 1080p 3D(1920x2160) @60Hz
- TMDS clock: 340MHz
- Content Protection : HDCP
- HDMI CTS Ver.1.4b Test(CTS 1.4b, October 11, 2011) : pass
Measurement: K28.5 3.0Gbps data input to ‘HDMI-Rx to HDMI Tx Chip’
MHL 2.1 Phy &Link silicon proven IP
- Data rate : 3Gbps
- Clock Speed : 75 MHz
- Resolution : Full HD 1080p @60Hz
- Mode : 24bit Pixel Mode, Packed Pixel Mode
- Audio : 7.1-Channel Surround-sound 지원
- HDCP (with error detection and correction by h/w)
- MHL CTS Version 1.2 Test : pass
DisplayPort 1.2a Phy &Link silicon proven IP
- Support 1, 2, or 4 lanes configuration
- Data rate : 5.4Gbps
- AUX Channel 1 MHz
- I2C over AUX Channel
- video format in RGB, YCbCr 4:4:4/4:2:2
- Deep color up to 16-bits per component
- HPD (hot plug detect) signal line
- stereo (two channel) 16 bit per sample LPCM
- DisplayPort CTS test : pass
보유 핵심 기술
Analog IP 및 설계 기술
- PLL(Phase Locked Loop)
- Serializer
- 송신Driver
- 수신Amp
- Equalizer
- CDR(Clock Data Recovery)
- De-serializer
- DLL(Delay Locked Loop)
- ESD보호 회로
Digital IP
- HDMI protocol Link RTL IP
- MHL protocol Link RTL IP
- DisplayPort protocol Link RTL IP
- USI-T protocol Link RTL IP
- USI-GF protocol Link RTL IP
- LVDS protocol Link RTL IP